Menu

VLSI Project Titles

    DIGITAL CMOS VLSI USING TANNER EDA TOOL

  1. Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates
  2. Low Power 4×4 Bit Multiplier Design using Dadda Algorithm and Optimized Full Adder.
  3. High speed and low power preset-able modified TSPC D flip-flop design and performance comparison with TSPCD flip-flop
  4. Designing of Multiplexer and De-Multiplexer Using Different Adiabatic Logic in 90nm Technology
  5. Arithmetic Logic Unit Using Diode Free Adiabatic Logic and Selection Unit for Adiabatic Logic Family
  6. Design Of Area Efficient And Low Power 4-Bit Multiplier Based On Full-swing GDI technique.
  7. Design of Swing Dependent XOR-XNOR Gates based Hybrid Full Adder
  8. Power Efficient Design of Adiabatic Approach for Low Power VLSI Circuits
  9. Delay Optimization of 4-Bit ALU Designed in FS-GDI Technique.
  10. Novel Self-Pipelining Strategy for Efficient Multiplication
  11. FPGA BASED DESIGN USING VIVADO HLS/XILINIX 12.4/ALTERA/MATLAB SIMULINK/DIGITAL SIGNAL PROCESSING – FIR/FFT/DWT/DCT

  12. Low power VLSI transposed structure FIR Filter using shift/add architecture
  13. Design and analysis of FIR filters using low power multiplier and full adder cells
  14. Area and Power Efficient VLSI Architecture of Distributed Arithmetic Based LMS Adaptive Filter
  15. A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO
  16. VLSI design of low-cost and high-precision fixed- reconfigurable FFT processors
  17. An Efficient Design of 16 Bit MAC Unit using Vedic Mathematics
  18. Design and Analysis of Area and Power Efficient Approximate Booth Multipliers
  19. Implementation of an XOR Based 16-bit Carry Select Adder for Area, Delay and Power Minimization.
  20. Direct and transposed form FIR FILTER using efficient multiplier and adders
  21. COGNITIVE RADIO/MIMO/ OFDM

  22. OFDM Based Wireless Powered Communication for Cooperative Relay System
  23. Successive Multipath Interference Cancellation for CP Free OFDM Systems
  24. Low Complexity ZF Receiver Design for Multi-User GFDMA Uplink Systems
  25. Resource Allocation in Heterogeneous Cognitive Radio Network with Non-orthogonal Multiple Access
  26. Cognitive MIMO Two-Way Relay Network: Joint Optimal Relay Selection and Spectrum Allocation
  27. Physical Layer Security of Interference-Limited Land Mobile Satellite Communication Systems
  28. Hybrid Carrier Underwater Acoustic Communication Based on Joint Time-Frequency Domain Equalization
  29. Effective Resource Utilization Schemes for Decode-and Forward Relay Networks With NOMA
  30. Interference-Free Hybrid Optical OFDM with Low-Complexity Receiver for Wireless Optical Communications
  31. Novel MIMO Detection With Improved Complexity for Near-ML Detection in MIMO-OFDM Systems
  32. REVERSIBLE LOGIC

  33. High Performance Division Circuit using Reversible Logic Gates
  34. Efficient Modular Adders based on Reversible
  35. Efficient Modular Adders based on Reversible Circuits
  36. CRYPTOGRAPHY

  37. An Efficient Fault Detection Scheme for Advanced Encryption Standard
  38. Modified Advanced Encryption Standard for Resource Constraint Environments
  39. Architecture Optimization and Performance Comparison of Nonce-Misuse-Resistant Authenticated Encryption Algorithms
  40. A High Performance, Low Energy, Compact Masked 128-Bit AES in 22nm CMOS Technology
  41. A Further Optimized Mix Column Architecture Design for the Advanced Encryption Standard
  42. FAULT INJECTION AND DETECTION

  43. Test Pattern Generation using NLFSR for Detecting Single tuck-at Faults
  44. Efficient Protection of the Register File in Soft-processors Implemented on Xilinx FPGAs
  45. A Novel Approach to Design Low Power and High Speed Self-Repairing Full Adder Circuit
  46. A Novel Approach to Design Low Power Self Repairing Full Adder Circuit
  47. PWM

  48. FPGA Based Modified Space Vector PWM technique for induction motor drive
  49. Performance Analysis of Conventional and Digital PWM Control Scheme for Speed Control of BLDC Motor Drives
  50. An Efficient DSP-FPGA-Based Implementation of Hybrid PWM for Electric Rail Traction Induction Motor Control
  51. QUANTUM-DOT CELLUAR AUTOMATA(QCA)

  52. Binary To Gray Code Converter Implementation Using QCA
  53. Novel Design of Flip-Flop Circuits using Quantum Dot Cellular Automata (QCA).
  54. SoC/NoC

  55. MALOC: A Fully Pipelined FPGA Accelerator for Convolutional Neural Networks With All Layers Mapped on Chip
  56. High-Performance NoC Simulation Acceleration framework employing the Xilinx DSP48E1 blocks
  57. COMPRESSION TECHNIQUES

  58. Efficient VLSI architecture for the parallel dictionary LZW data compression algorithm
  59. Efficient Compression-Based Line Buffer Design for Image/Video Processing Circuits


Clients

Enquiry